Senior Principal Solutions Engineer, RTL-to-GDS Implementation

Role Overview

Support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. Focus on RTL to GDSII delivery of projects, including implementation in multiple technology nodes on standard foundry solutions.

What You Will Do

Articulate design methodologies involving Cadence tools, implement RTL to GDSII delivery of projects, and participate in competitive benchmarking on complex blocks.

Why It Might Be a Fit

Gain experience in methodology, product delivery, and working on cutting-edge technology, with opportunities to innovate with Low Power and Multi-Voltage Design Techniques and work with leading edge Wireless and Mobile Customers.

Requirements

• 7+ years experience
• Strong technical knowledge of company products
• Design experience in ASIC design using industry-standard hardware description languages (Verilog)
• Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis)
• Experience with Low Power and Multi-Voltage Design Techniques